搜索资源列表
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
Verilog_Hdl48FIR
- verilog hdl fir 48阶-verilog hdl fir
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
fir
- 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
fir
- 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
halfband
- verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
coeff_rom_0_7
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
beta
- Fir verilog code implemented to find out the output of fir filter
FIR
- This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
fir
- 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FIR
- FIR filter using verilog code
FIR
- fir滤波器的简单实现，主要用于学习与理解(Simple implementation of the fir filter, mainly for learning and understanding)
FIR设计实现sgh
- FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)